MEAM.Design - ATmega32 Programming - Timers/Counters - Timer 3 Configuration Details


Timer 3 is a 16-bit free-running timer with one output compare unit, and a single input capture unit. The output compare pin is OC3A, and is multiplexed to C6, while the input capture pin is IPC3, which is multiplexed to C7.

Important Registers

TCNT3H + TCNT3L   timer/counter 3 value (high + low byte)
TCCR3A   timer/counter 3 control register A
TCCR3B   timer/counter 3 control register B
OCR3H + OCR3L   timer/counter 3 output compare register A (high + low byte)
ICR3H + ICR3L   timer/counter 3 input capture register (high + low byte)
TIFR3   timer/counter 3 interrupt flags



Clock Source - The default clock source for Timer 3 is the system clock. You can set the prescaler by modifying CS30, CS31, and CS32 in TCCR3B:

TCCR3B:
CS32
TCCR3B:
CS31
TCCR3B:
CS30
Prescaler
0 0 0  Clock Source Off
0 0 1  /1
0 1 0  /8
0 1 1  /64
1 0 0  /256
1 0 1  /1024



Timer Modes (Waveform Generation) - The timer can operate in a number of different modes, the most useful of which are listed here. The operation is controlled by setting WGM30, WGM31, WGM32, and WGM33 bits spread across TCCR3A and TCCR3B. The mode controls how the timer will count (either UP or UP/DOWN), what the maximum value will be, and whether to drive the output compare pin(s). Once the maximum value is reached, the timer will either reset to 0x0000 and continue counting (UP modes), or will reverse direction (UP/DOWN modes).

TCCR3B:
WGM33
TCCR3B:
WGM32
TCCR3A:
WGM31
TCCR3A:
WGM30
Function
Normal: Timer UP to a value, reset to 0x0000:
0 0 0 0  (mode 0) UP to 0xFFFF (16-bit)
0 1 0 0  (mode 4) UP to OCR3A
1 1 0 0  (mode 12) UP to ICR3
Single-Slope: Timer UP to a value, reset to 0x0000 (set/reset PWM):
0 1 0 1  (mode 5) UP to 0x00FF (8-bit), PWM mode
0 1 1 1  (mode 7) UP to 0x03FF (10-bit), PWM mode
1 1 1 0  (mode 14) UP to ICR3, PWM mode
Dual-Slope: Timer UP to a value, DOWN to 0x0000 (set/reset PWM):
0 0 0 1  (mode 1) UP to 0x00FF, DOWN to 0x0000, PWM mode
0 0 1 1  (mode 3) UP to 0x03FF, DOWN to 0x0000, PWM mode
1 0 1 0  (mode 10) UP to ICR3, DOWN to 0x0000, PWM mode



Channel A Compare Output (OC3A) Options - OC3A is multiplexed onto C6, which means that you must first set bit 6 of DDRC to enable output. The behavior of the OC3A output is then controlled in the TCCR3A register and is subject to one of the following:

When operating in modes 0 or 12, a match between TCNT3 and OCR3A will yield the following:

TCCR3A:
COM3A1
TCCR3A:
COM3A0
Function
0 0   no change
0 1   toggle
1 0   clear
1 1   set


When operating in modes 5, 7, or 14, a match between TCNT3 and OCR3A will yield the following:

TCCR3A:
COM3A1
TCCR3A:
COM3A0
Function
0 0   no change
1 0   clear at OCR3A, set at rollover
1 1   set at OCR3A, clear at rollover


When operating in modes 1, 3, or 10, a match between TCNT3 and OCR3A will yield the following:

TCCR3A:
COM3A1
TCCR3A:
COM3A0
Function
0 0   no change
1 0   clear at OCR3A during UP, set at OCR3A during DOWN
1 1   set at OCR3A during UP, clear at OCR3A during DOWN



Channels B & C - Though they cannot be used to change the state of an output pin, there are two other compare channels, B and C, which can be used to trigger interrupts with precise timing. The configuration of these two channels is essentially the same as Channels B and C in Timer 1.



Input Capture - When not in use as the TOP value for the timer, the input capture feature allows you to store the timer value into the ICR3 register at the instant when the ICP3 pin changes value. ICP3 is multiplexed with C7, so you must clear bit 7 of DDRC to make this an input. You can select whether to capture rising or falling edges by setting the ICES3 bit in the TCCR3B register:

TCCR3B:
ICES3
Function
0   store timer value on falling edge (default)
1   store timer value on rising edge



Flags - There are five flags within the TIFR3 register that can be used to monitor Timer 3:

TIFR3 : OCF3A   set when TCNT3 matches OCR3A
TIFR3 : OCF3B   set when TCNT3 matches OCR3B
TIFR3 : OCF3C   set when TCNT3 matches OCR3C
TIFR3 : ICF3   set whenever an input capture event takes place
TIFR3 : TOV3   set whenever TCNT3 returns to 0x0000

These can be cleared by writing a logic 1 to the register bit (e.g.: set(TIFR3,TOV3) to clear the overflow flag)



Interrupts

There are five interrupt vectors associated with Timer 3:

To call an interrupt whenever Timer 3 overflows (rolls over to 0x0000 after having reached 0xFFFF), set the TIMSK3 : TOIE3 bit, and write a handler for the TIMER3_OVF interrupt vector.

To call an interrupt whenever (TCNT3 matches OCR3A), set the TIMSK3 : OCIE3A bit, and write a handler for the TIMER3_COMPA interrupt vector.

To call an interrupt whenever (TCNT3 matches OCR3B), set the TIMSK3 : OCIE3B bit, and write a handler for the TIMER3_COMPB interrupt vector.

To call an interrupt whenever (TCNT3 matches OCR3C), set the TIMSK3 : OCIE3C bit, and write a handler for the TIMER3_COMPC interrupt vector.

To call an interrupt whenever an input capture event occurs, set the TIMSK3 : ICIE3 bit, and write a handler for the TIMER3_CAPT interrupt vector.

And do not forget to enable global interrupts, as discussed here.

Note that entering any of these interrupts will automatically clear the coresponding TIFR3 flag.



(A note on working with 16-bit concatenated registers: While the C compiler will handle all access issues for you, if you want to write code in assembly, you must write to the high byte first, then the low byte, and when reading, you must read the low byte first, then the high byte.)