MEAM.Design - ATmega32 Programming - Timers/Counters - Timer 0 Configuration Details
Timer 0 is an 8-bit free-running timer with two independent output compare units and PWM support. The output compare pins are OC0A and OC0B, which are multiplexed to B7 and D0.
Important Registers
| TCNT0 | timer/counter 0 value |
| TCCR0A | timer/counter 0 control register A |
| TCCR0B | timer/counter 0 control register B |
| OCR0A | timer/counter 0 output compare register A |
| OCR0B | timer/counter 0 output compare register B |
| TIFR0 | timer/counter 0 interrupt flags |
Clock Source - The default clock source for Timer 0 is the system clock. You can set the prescaler by modifying CS00, CS01, and CS02 in TCCR0B:
| TCCR0B: CS02 | TCCR0B: CS01 | TCCR0B: CS00 | Prescaler |
| 0 | 0 | 0 | OFF |
| 0 | 0 | 1 | /1 |
| 0 | 1 | 0 | /8 |
| 0 | 1 | 1 | /64 |
| 1 | 0 | 0 | /256 |
| 1 | 0 | 1 | /1024 |
Timer Modes (Waveform Generation) - The timer can operate in one of six modes, as set by the WGM00, WGM01, and WGM02 bits spread across TCCR0A and TCCR0B. The mode controls how the timer will count (either UP or UP/DOWN), what the maximum value will be (either 0xFF or whatever is in OCR0A), and whether to drive the output compare pin(s). Once the maximum value is reached, the timer will either reset to 0x00 and continue counting (UP modes), or will reverse direction (UP/DOWN modes).
| TCCR0B: WGM02 | TCCR0A: WGM01 | TCCR0A: WGM00 | Mode |
| 0 | 0 | 0 | UP to 0xFF |
| 0 | 1 | 0 | UP to OCR0A |
| 0 | 1 | 1 | UP to 0xFF, PWM mode |
| 1 | 1 | 1 | UP to OCR0A, PWM mode |
| 0 | 0 | 1 | UP to 0xFF, DOWN to 0x00, PWM mode |
| 1 | 0 | 1 | UP to OCR0A, DOWN to 0x00, PWM mode |
Channel A Compare Output (OC0A) Options - OC0A is multiplexed onto B7, which means that you must first set bit 7 of DDRB to enable output. The behavior of the OC0A output is then controlled in the TCCR0A register and is subject to one of the following:
When operating in UP to 0xFF mode, a match between TCNT0 and OCR0A will yield the following:
| TCCR0A: COM0A1 | TCCR0A: COM0A0 | Function |
| 0 | 0 | no change |
| 0 | 1 | toggle |
| 1 | 0 | clear |
| 1 | 1 | set |
When operating in UP to 0xFF, PWM mode, a match between TCNT0 and OCR0A will yield the following:
| TCCR0A: COM0A1 | TCCR0A: COM0A0 | Function |
| 0 | 0 | no change |
| 0 | 1 | no change |
| 1 | 0 | clear at OCR0A, set at 0xFF |
| 1 | 1 | set at OCR0A, clear at 0xFF |
When operating in UP to 0xFF, DOWN to 0x00, PWM mode, a match between TCNT0 and OCR0A will yield the following:
| TCCR0A: COM0A1 | TCCR0A: COM0A0 | |
| 0 | 0 | no change |
| 0 | 1 | no change |
| 1 | 0 | clear at OCR0A during UP, set at OCR0A during DOWN |
| 1 | 1 | set at OCR0A during UP, clear at OCR0A during DOWN |
Channel B Compare Output (OC0B) Options - OC0B is multiplexed onto D0, which means that you must first set bit 0 of DDRD to enable output. The behavior of the OC0B output is then controlled in the TCCR0A register and is subject to one of the following:
When operating in UP to 0xFF or UP to OCR0A mode, a match between TCNT0 and OCR0B will yield the following:
| TCCR0A: COM0B1 | TCCR0A: COM0B0 | Function |
| 0 | 0 | no change |
| 0 | 1 | toggle |
| 1 | 0 | clear |
| 1 | 1 | set |
When operating in UP to 0xFF, PWM mode, a match between TCNT0 and OCR0B will yield the following:
| TCCR0A: COM0B1 | TCCR0A: COM0B0 | |
| 0 | 0 | no change |
| 1 | 0 | clear at OCR0B, set at 0xFF |
| 1 | 1 | set at OCR0B, clear at 0xFF |
When operating in UP to OCR0A, PWM mode, a match between TCNT0 and OCR0B will yield the following:
| TCCR0A: COM0B1 | TCCR0A: COM0B0 | Function |
| 0 | 0 | no change |
| 1 | 0 | clear at OCR0B, set at OCR0A |
| 1 | 1 | set at OCR0B, clear at OCR0A |
When operating in UP to 0xFF, DOWN to 0x00, PWM mode or UP to OCR0A, DOWN to 0x00, PWM mode, a match between TCNT0 and OCR0A will yield the following:
| TCCR0A: COM0B1 | TCCR0A: COM0B0 | Function |
| 0 | 0 | no change |
| 1 | 0 | clear at OCR0B during UP, set at OCR0B during DOWN |
| 1 | 1 | set at OCR0B during UP, clear at OCR0B during DOWN |
Flags - There are three flags within the TIFR0 register that can be used to monitor Timer 0:
| TIFR0 : OCF0A | set when TCNT0 matches OCR0A |
| TIFR0 : OCF0B | set when TCNT0 matches OCR0B |
| TIFR0 : TOV0 | set whenever TCNT0 returns to 0x00 |
These can be cleared by writing a logic 1 to the register bit (e.g.: set(TIFR0,TOV0) to clear the overflow flag)
Interrupts
There are three interrupt vectors associated with Timer 0:
To call an interrupt whenever Timer 0 overflows (returns to 0x00), set the TIMSK0 : TOIE0 bit, and write a handler for the TIMER0_OVF interrupt vector.
To call an interrupt whenever (TCNT0 matches OCR0A), set the TIMSK0 : OCIE0A bit, and write a handler for the TIMER0_COMPA interrupt vector.
To call an interrupt whenever (TCNT0 matches OCR0B), set the TIMSK0 : OCIE0B bit, and write a handler for the TIMER0_COMPB interrupt vector.
And do not forget to enable global interrupts, as discussed here.
Note that entering any of these interrupts will automatically clear the coresponding TIFR0 flag.